LTM8046 [Linear Systems]
Dual SEPIC or Inverting Module DC DC Converter;型号: | LTM8046 |
厂家: | Linear Systems |
描述: | Dual SEPIC or Inverting Module DC DC Converter |
文件: | 总18页 (文件大小:1690K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM8049
Dual SEPIC or Inverting
µModule DC/DC Converter
FEATURES
DESCRIPTION
TheLTM®8049isaDualSEPIC/InvertingµModule® (power
module) DC/DC Converter. Each of the two outputs can
be easily configured as a SEPIC or Inverting converter by
simplygroundingtheappropriateoutputrail.TheLTM8049
includes power devices, inductors, control circuitry and
passive components. All that is needed to complete the
design are input and output caps, and small resistors to
set the output voltages and switching frequency. Other
components may be used to control the soft-start and
undervoltage lockout.
n
Two Complete Switch Mode Power Supplies
n
SEPIC or Inverting Topology
n
Wide Input Voltage Range: 1.6V to 10V
n
1.5V to 14V or –1.5V to –14V Output Voltage
n
±A at 5V
from ±1V
OUT
IN
n
n
n
n
n
Selectable Switching Frequency: 100kHz to 1.5MHz
Power Good Outputs for Event Based Sequencing
User Configurable Undervoltage Lockout
(e4) RoHS Compliant Package with Gold Pad Finish
Low Profile 15mm × 9mm × 2.42mm Surface Mount
BGA Package
The LTM8049 is packaged in a thermally enhanced, com-
pact (15mm × 9mm) over-molded Ball Grid Array (BGA)
packagesuitableforautomatedassemblybystandardsur-
face mount equipment. The LTM8049 is RoHS compliant.
APPLICATIONS
n
Battery Powered Regulator
n
Local Negative Voltage Regulator
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
n
Low Noise Amplifier Power
TYPICAL APPLICATION
±±1VOUT from 1.7VIN to 10VIN
Maximum Load Current vs VIN
1.5
V
V
OUT1P
IN1
V
V
OUT1
IN
2.7V TO 20V
12V
4.7µF
FBX1
RUN1
×2
130k
V
OUT1N
RT1
1.0
0.5
0
22µF
80.6k
1MHz
CLKOUT1
SYNC2
RT2
LTM8049
80.6k
1MHz
V
V
OUT2P
IN2
47µF
FBX2
RUN2
143k
V
OUT2N
V
OUT2
SYNC1
–12V
0
5
10
(V)
15
20
V
IN
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2, SHARE1, SHARE2
8049 TA01a
8049 TA01
8049f
1
For more information www.linear.com/LTM8049
LTM8049
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note ±)
TOP VIEW
V
, RUNn, PGn.......................................................20V
INn
BANK 2
SYNCn, FBXn ..............................................................5V
SSn..........................................................................2.5V
SHAREn ......................................................................2V
A
V
BANK 4
OUT1P
IN1
V
B
C
D
E
F
RUN1
SS1
BANK 1
GND
FBX1
PG1
V
V
(V
= 0V)..................................................25V
= 0V)................................................–25V
OUTP OUTN
SYNC1
RT1
BANK 6
CLKOUT1
SHARE2
(V
OUTN OUTP
V
OUT1N
Maximum Internal Temperature............................ 125°C
Maximum Solder Temperature..............................260°C
Storage Temperature.............................. –55°C to 125°C
SHARE1
G
H
J
RT2
BANK 7
OUT2N
CLKOUT2
V
SYNC2
SS2
PG2
FBX2
K
L
RUN2
BANK 5
OUT2P
V
BANK 3
V
IN2
1
2
3
4
5
6
7
BGA PACKAGE
77-LEAD (15mm × 9mm × 2.42mm)
T
= 125°C, θ = 16.2°C/W, θ = 3.8°C/W, θ
= 8.8°C/W,
JMAX
θ
JA
JB
JCtop
= 3.8°C/W, θ
= 4.6°C/W, WEIGHT = 0.8g,
JCbottom
JCboard
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
(http://www.linear.com/product/LTM8049#orderinfo)
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 1)
PART NUMBER
LTM8049EY#PBF
LTM8049IY#PBF
PAD OR BALL FINISH
DEVICE
FINISH CODE
–40°C to 125°C
–40°C to 125°C
SAC305 (RoHS)
LTM8049Y
e1
BGA
3
* Device temperature grade is indicated by a label on the shipping container. • Recommended BGA PCB Assembly and Manufacturing Procedures:
www.linear.com/BGA-assy
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings: www.linear.com/packaging
• Terminal Finish Part Marking: www.linear.com/leadfree
• This product is moisture sensitive. For more information, go to:
• This product is not recommended for second side reflow. For more
www.linear.com/BGA-assy
information, go to www.linear.com/BGA-assy
8049f
2
For more information www.linear.com/LTM8049
LTM8049
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range (Notes 1, 3), otherwise specifications are at TA = 15°C. RUN = 1V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
Minimum Input Operating Voltage
Positive Output DC Voltage
2.6
V
I
I
= 50mA, R = 15.4k, V
Grounded
OUTN
Grounded
OUTN
2.5
24
V
V
OUT
OUT
FB
= 50mA, R = 274k, V
FB
Negative Output DC Voltage
I
I
= 50mA, R = 30.1k, V
Grounded
OUTP
Grounded
OUTP
–2.5
–24
V
V
OUT
OUT
FB
= 50mA, R = 287k, V
FB
Maximum Continuous Output DC Current
V
V
= 12V, V
= 12V, V
= 5V or –5V
= 24 or –24V
1
0.25
A
A
IN
IN
OUT
OUT
V
Quiescent Current
V
RUN
V
RUN
= 0V
= 2V, No Load
0
10
2
µA
mA
IN
Line Regulation
4 ≤ V ≤ 20V, I
= 0.6A
0.1
0.3
%
%
IN
OUT
Load Regulation
Switching Frequency
0 ≤ I
≤ 1A
OUT
l
l
R = 31.6k
2100
160
2500
200
2900
240
kHz
kHz
T
R = 412k
T
l
l
Voltage at FBX Pin
Positive Output
Negative Output
1.185
2
1.204
7
1.22
16
V
mV
l
l
Current into FBX Pin
RUN pin Threshold Voltage
RUN Pin Current
Positive Output
Negative Output
81
81
83.3
83.3
85.6
85.6
µA
µA
RUN Pin Rising
RUN Pin Falling
1.31
1.27
1.4
V
V
1.21
10.1
V
RUN
V
RUN
V
RUN
= 3V
= 1.3V
= 0V
45
12.1
0
65
14.1
0.1
µA
µA
µA
SS Sourcing Current
SS = 0V
5.7
8.8
11.7
2500
0.4
µA
kHz
V
Synchronization Frequency Range
SYNC Input Low Threshold
SYNC Input High Threshold
CLKOUT1 Duty Cycle
200
1.3
V
(Note 5)
50
%
CLKOUT Output Voltage (Low)
CLKOUT Output Voltage (High)
PG Threshold for Positive Feedback Voltage
PG Threshold for Negative Feedback Voltage
PG Output Voltage Low
2k Pull-Up to 2V
0.2
V
2k Pull-Down to GND
FBX Rising
1.9
1.09
20
V
1.2
120
150
1
V
FBX Falling
mV
mV
µA
100µA into PG, FBX = 1V
PG = 20V, Run = 0V
PG Leakage Current
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 1: The LTM8049E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C internal
temperature range are assured by design, characterization and correlation
with statistical process controls. LTM8049I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum internal temperature is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
Note 3: This μModule regulator includes overtemperature protection that
is intended to protect the device during momentary overload conditions.
Internal temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum internal
operating junction temperature may impair device reliability.
Note 4: CLKOUTn is intended to drive other circuitry. Do not apply a
positive or negative voltage or current source to CLKOUT, otherwise
permanent damage may occur.
Note 5: The duty cycle of CLKOUT2 is dependent upon the internal
temperature. See the Applications Information section for more details.
8049f
3
For more information www.linear.com/LTM8049
LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT ±2.5V
Efficiency, VOUT ±3.3V
Efficiency, VOUT ±5V
75
65
55
45
75
65
55
45
80
70
60
50
5V
IN
IN
IN
12V
5V
8V
5V
IN
IN
IN
IN
15V
12V
0
0.5
1
1.5
2
0
0.5
1
1.5
2
0
0.5
1
1.5
2
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8049 G01
8049 G02
8049 G03
Efficiency, VOUT ±8V
Efficiency, VOUT ±12V
Efficiency, VOUT ±15V
85
75
65
55
85
75
65
55
85
75
65
55
5V
IN
IN
IN
5V
IN
IN
IN
5V
IN
IN
IN
12V
12V
12V
16V
16V
16V
0
0.5
1
1.5
0
0.50
1
1.50
0
0.25
0.50
0.75
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8049 G04
8049 G05
8049 G06
Efficiency, VOUT ±18V
Efficiency, VOUT ±24V
Input vs Load Current, VOUT ±2.5V
85
75
65
55
85
75
65
55
2.5
2.0
1.5
1.0
0.5
0
5V
IN
IN
IN
5V
IN
IN
IN
12V
5V
8V
12V
IN
IN
16V
16V
0
0.20
0.40
0.60
0.80
0
0.2
0.4
0.6
0
0.5
1
1.5
2
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8049 G07
8049 G08
8049 G09
8049f
4
For more information www.linear.com/LTM8049
LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
Input vs Load Current, VOUT ±3.3V
Input vs Load Current, VOUT ±5V
Input vs Load Current, VOUT ±8V
2.5
2.0
1.5
1.0
0.5
0
3.0
2.0
1.0
0
3.0
2.0
1.0
0
5V
5V
IN
IN
IN
IN
5V
IN
IN
12V
12V
IN
IN
12V
16V
15V
0
0.5
1
1.5
2
0
0.5
1
1.5
2
0
0.5
1
1.5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8049 G10
8049 G11
8049 G12
Input vs Load Current, VOUT ±12V
Input vs Load Current, VOUT ±15V
Input vs Load Current, VOUT ±18V
3.0
2.0
1.0
0
3.0
2.0
1.0
0
3.0
2.0
1.0
0
5V
IN
IN
IN
5V
5V
IN
IN
IN
IN
IN
IN
12V
12V
12V
16V
16V
16V
0
0.25
0.50
0.75
1
0
0.50
1
1.50
0
0.2
0.4
0.6
0.8
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8049 G14
8049 G13
8049 G15
Input vs Load Current, VOUT ±24V
Maximum Load Current vs VIN
Maximum Load Current vs VIN
3.0
2.0
1.0
0
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
PER CHANNEL
PER CHANNEL
5V
2.5V
3.3V
5V
8V
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
12V
12V
16V
15V
0
0.2
0.4
0.6
0
5
10
15
0
5
10
(V)
15
20
LOAD CURRENT (A)
V
(V)
V
IN
IN
8049 G16
8049 G17
8049 G18
8049f
5
For more information www.linear.com/LTM8049
LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Load Current vs VIN
Derating Curve, VOUT ±2.5VOUT
Derating Curve, VOUT ±3.3VOUT
1.00
0.75
0.50
0.25
0
2.00
1.50
1.00
0.50
0
2.00
1.50
1.00
0.50
0
PER CHANNEL
0LFM
0 LFM
18V
24V
OUT
OUT
5V
8V
5V
IN
12V
IN
IN
IN
0
5
10
(V)
15
20
0
25
50
75
100
125
0
25
50
75
100
125
V
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
IN
8049 G19
8049 G20
8049 G21
Derating Curve, VOUT ±5VOUT
Derating Curve, VOUT ±8VOUT
Derating Curve, VOUT ±12VOUT
2.00
1.50
1.00
0.50
0
1.50
1.00
0.50
0
1.50
1.00
0.50
0
0 LFM
0 LFM
0 LFM
5V
5V
5V
IN
IN
IN
IN
IN
IN
IN
12V
12V
12V
16V
IN
IN
16V
15V
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8049 G22
8049 G23
8049 G24
Derating Curve, VOUT ±15VOUT
Derating Curve, VOUT ±18VOUT
Derating Curve, VOUT ±24VOUT
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
0.75
0.50
0.25
0
0 LFM
0 LFM
0 LFM
5V
5V
IN
5V
IN
IN
IN
IN
IN
IN
12V
12V
16V
12V
IN
IN
16V
16V
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8049 G25
8049 G26
8049 G27
8049f
6
For more information www.linear.com/LTM8049
LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
Output Ripple, DC2244A Board
800mA Load, 12VIN
Measured Across C5, C6
CLKOUT2 Duty Cycle
vs Temperature
80
f
= 1MHz
SW
12V
OUT
50mV/DIV
60
40
20
–12V
OUT
20mV/DIV
8049 G29
500ns/DIV
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
8049 G28
PIN FUNCTIONS
GND (Bank 1): Tie these GND pins to a local ground plane
RUN1,RUN2(PinsB7,K7):Thesepinsareusedtoenable/
disable the chip and restart the soft-start sequence. Drive
below 1.21V to stop the LTM8049 from switching. Drive
above 1.4V to activate the device and restart the soft-start
sequence. Do not float this pin.
below the LTM8049 and the circuit components. GND
MUST BE CONNECTED EITHER TO V
OR V
FOR
OUTP
OUTN
PROPER OPERATION. In most applications, the bulk of
the heat flow out of the LTM8049 is through these pads,
so the printed circuit design has a large impact on the
thermal performance of the part. See the PCB Layout and
Thermal Considerations sections for more details. Return
the feedback divider (RFB) to this net.
RT1,RT2(PinsE7,G7):TheRTnpinsareusedtoprogram
the switching frequency of the LTM8049 by connecting a
resistor from this pin to ground. The switching frequency
of the LTM8049 is determined by the equation RTn =
V
, V (Banks 2, 3): The V pins supply current to
IN1 IN2
(81.6/f )-1, wherethef
istheswitchingfrequencyin
INn
OSC
OSC
theLTM8049’sinternalregulatorandtotheinternalpower
switch. Thispinmustbelocallybypassedwithanexternal,
low ESR capacitor.
MHz. This pin must have a resistor to GND. Do not apply
a voltage to this pin.
SS1, SS2 (Pins C7, J7): Connect a soft-start capacitor
from this pin to GND. Upon start-up, the SSn pins will be
charged by an internal current source to about 2V.
V
, V
(Banks 4, 5): V
is the positive out-
OUTnP
OUT1P OUT2P
put of the LTM8049. Apply an external capacitor between
V
and V . Tie this net to GND to configure the
OUTnP
OUTnN
SYNC1, SYNC2(PinsD7, H7):Tosynchronizetheswitch-
ingfrequencytoanoutsideclock,simplydrivethispinwith
a clock signal. The high voltage level of the clock needs
to exceed 1.3V, and the low level must be less than 0.4V.
Drive this pin to less than 0.4V to revert to the internal
free running clock. Ground these pins if synchronization
is not required. See the Applications Information section
for more information.
LMT8049 as a negative output Inverting regulator.
V
, V (Banks 6, 7): V is the negative out-
OUT1N OUT2N
put of the LTM8049. Apply an external capacitor between
OUTnP
OUTnN
V
and V . Tie this net to GND to configure the
OUTnN
LTM8049 as a positive output SEPIC regulator.
8049f
7
For more information www.linear.com/LTM8049
LTM8049
PIN FUNCTIONS
FBX1, FBX2 (Pins C1, J1): If configured as a SEPIC, the
LTM8049 regulates its FBX pin to 1.204V. Apply a resis-
CLKOUT1, CLKOUT2 (Pins E6, G6): Use these pins to
synchronize devices to either channel of the LTM8049.
ThesepinsoscillateatthesamefrequencyastheLTM8049
internaloscillatoror, ifactive, theSYNCpin. TheCLKOUT1
signal is about 180° out of phase with the oscillator of
channel1anddutycycleisabout50%.TheCLKOUT2signal
is in phase with the internal oscillator of channel 2 and its
duty cycle varies linearly with the internal temperature of
theLTM8049. PleaserefertotheApplicationsInformation
section for detailed information on using CLKOUT2 as an
indication of the LTM8049 internal temperature. Do not
apply a voltage to this pin or use this pin to drive capaci-
tive loads greater than 120pF.
tor between FBX and V
. Its value should be R
=
OUTP
FB
[(V
– 1.204)/0.0833]k. If the LTM8049 is configured
OUTP
as an inverting converter, the LTM8049 regulates the FBX
pin to 7mV. Apply a resistor between FBX and V of
OUTN
value R = [(|V
| + 0.007)/0.0833]k. The LTM8049
OUTN
FB
features frequency foldback to protect the power switches
during a fault or output current overload. During start-up,
frequency foldback also limits the current the LTM8049
delivers to the load. The user must evaluate the start-up
behavior of the LTM8049 to ensure that it properly pow-
ers up the load.
PG1, PG2 (Pins D6, H6): These active high pins indicates
that the FBn pin voltage for the corresponding channel
is within 4% of its regulation voltage These open drain
outputsrequiresapull-upresistortoindicatepowergood.
Also, the status of these pins is valid only when RUN >
SHARE1, 2 (pins F3, F4): Connect these pins together if
thetwooutputsoftheLTM8049areparalleled. Otherwise,
leave these pins floating.
1.4V and V > 2.6V.
IN
BLOCK DIAGRAM
2.2µF
4.7µH
V
V
OUT1P
IN1
0.1µF
4.7µH
V
OUT1N
RUN1
RT1
FBX1
PG1
CONTROLLER
SHARE1
SYNC1
CLKOUT1
GND
8049 BD
NOTE: CHANNEL 1. CHANNEL 2 IS FUNCTIONAL IDENTICAL, EXCEPT FOR THE CLKOUT2
VS TEMPERATURE BEHAVIOR. PLEASE SEE THE PIN DESCRIPTION AND APPLICATIONS
INFORMATION SECTIONS FOR DETAILS.
8049f
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For more information www.linear.com/LTM8049
LTM8049
OPERATION
The LTM8049 contains two stand-alone switching DC/
DC converters; either one may be configured as a SEPIC
(single-ended primary inductance converter) or inverting
The LTM8049 also features RUN and SS pins to control
the start-up behavior of the device. The RUN pin may also
be used to implement an accurate undervoltage lockout
function by applying a resistor network to the RUN pin.
power supply simply by tying V
or V
to GND,
OUTN
OUTP
respectively. It accepts an input voltage up to 20VDC. The
output is adjustable between 2.5V and 24V for the SEPIC,
and between –2.5V and –24V for the inverting configura-
The LTM8049 features frequency foldback to protect the
power switches during a fault or output current overload.
Duringstart-up, frequencyfoldbackalsolimitsthecurrent
the LTM8049 delivers to the load. The user must evaluate
the start-up behavior of the LTM8049 to ensure that it
properly powers up the load.
tion. The LTM8049 can provide 1.5A at V = 12V when
IN
V
OUT
= 5V or –5V at ambient room temperature.
As shown in the Block Diagram, the LTM8049 contains a
current mode controller, power switching element, power
coupled inductor, power Schottky diode and a modest
amount of input and output capacitance. The LTM8049
is a fixed frequency PWM regulator.
The LTM8049 is equipped with a thermal shutdown to
protectthedeviceduringmomentaryoverloadconditions.
It is set above the 125°C absolute maximum internal tem-
perature rating to avoid interfering with normal specified
operation, so internal device temperatures will exceed
the absolute maximum rating when the overtemperature
protection is active. Therefore, continuous or repeated
activation of the thermal shutdown may impair device
reliability.
TheLTM8049switchingcanfreerunbyapplyingaresistorto
theRTpinorsynchronizetoanexternalsourceatafrequency
between 200kHz and 2.5MHz. To synchronize to an external
source, drive a valid signal source into the SYNC pin. See
SynchronizationintheApplicationsSectionformoredetails.
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
optimal efficiency over the given input condition is given
in the f
column. Running the LTM8049 faster than
OPTIMAL
the recommended frequency may reduce the usable input
voltage range.
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. ApplytherecommendedC , C , R andR values.
Capacitor Selection Considerations
IN OUT ADJ
T
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that the
maximum output current is limited by junction tempera-
ture, therelationshipbetweentheinputandoutputvoltage
magnitude and polarity and other factors. Please refer to
the graphs in the Typical Performance Characteristics
section for guidance.
The C and C
capacitor values in Table 1 are the
IN
OUT
minimum recommended values for the associated oper-
ating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Table 1 gives the recommended component values and
configuration for a single channel. Each channel may be
configured independently. The maximum frequency (and
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
attendant R value) at which the LTM8049 should be al-
T
lowed to switch is given in Table 1 in the f
column,
MAX
while the recommended frequency (and R value) for
voltage coefficients of capacitance. In an application
T
8049f
9
For more information www.linear.com/LTM8049
LTM8049
APPLICATIONS INFORMATION
Table 1. Recommended Component Values and Configuration (TA = 25°C)
V
RANGE (V)
V
OUT
(V)
C
IN
C
OUT
R
FB
(Ω)
f
R
(Ω)
f
R
TMIN
(Ω)
IN
OPTIMAL
TOPTIMAL
MAX
2.6V to 11.5V
2.6V to 9.5V
2.5V
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
100µF 4V 0805 X5R
15.4k
30.1k
600kHz
600kHz
137k
2MHz
2MHz
38.3k
38.3k
–2.5V
100µF 4V 0805 X5R
+ 47µF 6.3V 0805 X5R
137k
2.6V to 18V
2.6V to 12V
3.3V
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
100µF 4V 0805 X5R
25.5k
39.2k
650kHz
650kHz
124k
124k
2.3MHz
2.3MHz
33.2k
33.2k
–3.3V
100µF 4V 0805 X5R
+ 47µF 6.3V 0805 X5R
2.7V to 20V
2.7V to 15V
5V
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
47µF 6.3V 0805 X5R
45.3k
60.4k
750k
750k
107k
107k
2.5MHz
2.5MHz
31.6k
31.6k
–5V
100µF 6.3V 1206 X5R
+ 47µF 10V 1206 X5R
2.7V to 20V
2.7 to 18.5V
2.7V to 20V
2.7V to 20V
2.7V to 20V
2.7V to 20V
3V to 20V
8V
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
22µF 10V 1206 X5R
2x 47µF 10V 1206 X5R
22µF 16V 1210 X5R
47µF 16V 1210 X5R
22µF 16V 1210 X5R
47µF 16V 1210 X5R
22µF 16V 1210 X7R
22µF 16V 1210 X7R
22µF 25V 1206 X5R
22µF 25V 1206 X5R
82.5k
95.3k
130k
143k
165k
178k
200k
215k
274k
287k
1MHz
1MHz
80.6k
80.6k
80.6k
80.6k
73.2k
73.2k
53.6k
53.6k
53.6k
53.6k
2.5MHz
2.5MHz
2.5MHz
2.5MHz
1.9MHz
1.9MHz
1.8MHz
1.8MHz
1.8MHz
1.8MHz
31.6k
31.6k
31.6k
31.6k
41.2k
41.2k
45.3k
45.3k
45.3k
45.3k
–8V
12V
1MHz
–12V
15V
1MHz
1.1MHz
1.1MHz
1.5MHz
1.5MHz
1.5MHz
1.5MHz
–15V
18V
3V to 20V
–18V
24V
3.7V to 18V
3.7V to 18V
–24V
Note: An input bulk capacitor is required.
circuit they may have only a small fraction of their nominal
capacitanceresultinginmuchhigheroutputvoltageripple
than expected.
Switching Frequency Trade-Offs
ItisrecommendedthattheuserapplytheoptimalR value
T
given in Table 1 for the corresponding input and output
operatingcondition. Systemlevelorotherconsiderations,
however, may necessitate another operating frequency.
While the LTM8049 is flexible enough to accommodate
a wide range of operating frequencies, a haphazardly
chosen one may result in undesirable operation under
certain operating or fault conditions. A frequency that is
too high can reduce efficiency, reduce the usable input
voltage range, generate excessive heat or even damage
the LTM8049 in some fault conditions. A frequency that
is too low can result in a final design that has too much
output ripple or too large of an output capacitor. Note that
the Maximum Output Current vs Input Voltage curves
given in the Typical Characteristics section are for the
recommended operating conditions in Table 1. Using a
different operating frequency may result in a different
maximum output current.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8049. A
ceramic input capacitor combined with trace or cable
inductance forms a high Q (underdamped) tank circuit.
If the LTM8049 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Programming Switching Frequency
TheLTM8049hasanoperationalswitchingfrequencyrange
between 200kHz and 2.5MHz. The free running frequency
is programmed with an external resistor from the RT pin
to ground. Do not leave this pin open under any condition.
When the SYNC pin is driven low (<0.4V), the frequency
of operation is set by a resistor from RT to ground. The
R value is calculated by the following equation:
T
81.6
fOSC
RT =
–1, where fOSC is in MHz and RT is in kΩ
8049f
10
For more information www.linear.com/LTM8049
LTM8049
APPLICATIONS INFORMATION
Soft-Start
The RUN pin has a voltage hysteresis with typical thresh-
olds of 1.31V (rising) and 1.27V (falling). Resistor R
UVLO2
The soft-start circuitry provides for a gradual ramp-up of
the switch current in each channel. When the channel is
enabled, the external SS capacitor is first discharged. This
resets the state of the logic circuits in the channel. Then
an integrated resistor pulls the channel’s SS pin to about
1.8V. The LTM8049 has a built-in soft-start characteristic,
but a slower ramp rate may be implemented by adding
capacitance to the SS pin. Typical values are between
0.1µF and 1µF.
is optional. R
can be included to reduce the overall
UVLO2
UVLO voltage variation caused by variations in the RUN
pin current (see the Electrical Characteristics). A good
choice for R
is ≤10k + 1%. After choosing a value
can be determined from either of the
UVLO2
, R
for R
UVLO2 UVLO1
following:
V
IN(RISING) –1.31V
RUVLO1
=
=
1.32V
+12.1µA
RUVLO2
Configurable Undervoltage Lockout
or
Figure 1 shows how to configure an undervoltage lock-
out (UVLO) for the LTM8049. Typically, UVLO is used in
situations where the input supply is current-limited, has
a relatively high source resistance, or ramps up/down
slowly. A switching regulator draws constant power from
the source, so source current increases as source voltage
drops. This looks like a negative resistance load to the
source and can cause the source to current-limit or latch
low under low source voltage conditions. UVLO prevents
the regulator from operating at source voltages where
these problems might occur.
VIN(FALLING) –1.27V
RUVLO1
1.29V
+11.6µA
RUVLO2
where V
and V
are the V threshold
IN(FALLING) IN
IN(RISING)
voltages when rising or falling respectively.
For example, to disable the LTM8049 for V voltages
IN
below3.5Vusingthesingleresistorconfiguration,choose:
3.5V –1.27V
RUVLO1
=
≅191k
1.29V
LTM8049
+11.6µA
∞
V
V
IN
IN
1.31V
–
+
R
UVLO1
To activate the LTM8049 for V greater than 4.5V using
IN
ACTIVE/
LOCKOUT
RUN
the two resistor configuration, choose R
= 10k and:
UVLO2
12.3µA
AT 1.31V
R
UVLO2
(OPTIONAL)
4.5V –1.31V
RUVLO1
=
≅22.1k
GND
1.32V
+12.1µA
10k
8049 F01
Figure 1. The RUN Pin May Be Used to Implement
an Accurate UVLO
Internal Undervoltage Lockout
The LTM8049 monitors the V supply voltage in case V
IN
IN
The RUN pin sinks 12.1µA at the 1.31V rising threshold
voltage and about 11.6µA at the 1.27V falling threshold.
This makes it easy to set up an input voltage UVLO thresh-
drops below a minimum operating level (typically about
2.3V). When V is detected low, the power switch is
IN
deactivated, and while sufficient V voltage persists, the
IN
old with just a single resistor. For a desired V threshold,
IN
soft-start capacitor is discharged. After V is sufficiently
IN
choose R
using the equation:
UVLO1
high,theLTM8049willreactivateandthesoft-startcapaci-
V –1.31V
12.1µA
IN
tor will begin charging.
RUVLO1
=
8049f
11
For more information www.linear.com/LTM8049
LTM8049
APPLICATIONS INFORMATION
Frequency Foldback
that internal temperatures will exceed the 125°C absolute
maximum rating when the overtemperature protection is
active, possibly impairing the device’s reliability.
The frequency foldback function reduces the switching
frequency for that channel when the output is about 15%
below the target regulation point. This feature lowers the
operatingfrequency,thuscontrollingthemaximumoutput
current during start-up. When the FBX voltage is pulled
abovetheabovementionedrangeinapositiveoutputvolt-
age application, the switching frequency for that channel
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8049. The LTM8049 is neverthe-
less a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 2
for a suggested layout. Ensure that the grounding and
heat-sinking are acceptable.
runs that the rate set by the R resistor value. Note that
T
the maximum output current at start-up is a function of
many variables including load profile, output capacitance,
target V , V , switching frequency, so the user must
OUT IN
evaluate the performance of the LTM8049 to ensure that
it properly powers up its load.
A few rules to keep in mind are:
Thermal Shutdown
1. Place the R and R resistors as close as possible to
FBX
T
If the part is too hot, the LTM8049 engages its thermal
shutdown and terminates switching and discharges the
soft-startcapacitor.Whentheparthascooled,thepartauto-
maticallyrestarts.Thisthermalshutdownissettoengageat
temperaturesabovethe125°Cabsolutemaximuminternal
operating rating to ensure that it does not interfere with
functionality in the specified operating range. This means
their respective pins.
2. Place the C capacitor as close as possible to the V
IN
IN
and GND connection of the LTM8049.
3. Place the C
capacitor as close as possible to the
OUT
V
and GND connection of the LTM8049.
OUT
GND
V
V
IN1
IN2
RUN1 SS1 SYNC1 RT1
RT2 SYNC2 SS2 RUN2
PG1 CLKOUT1 CLKOUT2 PG2
C
C
IN1
GND
GND
SHARE2
SHARE1
IN2
FBX1
FBX2
C
C
OUT1
OUT2
V
V
OUT1
OUT2
GND
GND
(POSITIVE OUTPUT)
(NEGATIVE OUTPUT)
8049 F02
THERMAL/GND VIAS
Figure 2. Layout Showing Suggested External Components, GND Plane and Thermal Vias
8049f
12
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LTM8049
APPLICATIONS INFORMATION
4. Place the C and C
capacitors such that their
Thermal Considerations
IN
OUT
ground current flow directly adjacent or underneath
The LTM8049 output current may need to be derated if
it is required to operate in a high ambient temperature or
deliver a large amount of continuous power. The amount
of current derating is dependent upon the input voltage,
output power and ambient temperature. The temperature
rise curves given in the Typical Performance Character-
istics section can be used as a guide. These curves were
the LTM8049.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8049.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 2. The LTM8049 can benefit from
theheat-sinkingaffordedbyviasthatconnecttointernal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
2
generated by a LTM8049 mounted to a 58cm 4-layer FR4
printedcircuitboard. Boardsofothersizesandlayercount
can exhibit different thermal behavior, so it is incumbent
upon the user to verify proper operation over the intended
system’sline,loadandenvironmentaloperatingconditions.
The thermal resistance numbers listed in Page 2 of the
data sheet are based on modeling the µModule package
mounted on a test board specified per JESD51-9 (Test
Boards for Area Array Surface Mount Package Thermal
Measurements). The thermal coefficients provided in this
page are based on JESD 51-12 (Guidelines for Reporting
and Using Electronic Package Thermal Information).
Forincreasedaccuracyandfidelitytotheactualapplication,
many designers use FEA to predict thermal performance.
To that end, Page 2 of the data sheet typically gives four
thermal coefficients:
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8049. However, these capacitors
can cause problems if the LTM8049 is plugged into a live
input supply (see Application Note 88 for a complete dis-
cussion). The low loss ceramic capacitor combined with
stray inductance in series with the power source forms an
θ : Thermal resistance from junction to ambient
JA
θ
: Thermal resistance from junction to the bottom
JCbottom
of the product case
θ
: Thermal resistance from junction to top of the
JCtop
underdamped tank circuit, and the voltage at the V pin
IN
product case
of the LTM8049 can ring to more than twice the nominal
inputvoltage,possiblyexceedingtheLTM8049’sratingand
damaging the part. If the input supply is poorly controlled
or the user will be plugging the LTM8049 into an energized
supply,theinputnetworkshouldbedesignedtopreventthis
overshoot. This can be accomplished by installing a small
θ :Thermalresistancefromjunctiontotheprintedcircuit
JB
board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
resistor in series to V , but the most popular method of
IN
controlling input voltage overshoot is to add an electrolytic
θ
is the natural convection junction-to-ambient air
JA
bulkcapacitortotheV net. Thiscapacitor’srelativelyhigh
IN
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
equivalentseriesresistancedampsthecircuitandeliminates
the voltage overshoot. The extra capacitor improves low
frequency ripple filtering and can slightly improve the ef-
ficiency of the circuit, though it is physically large.
8049f
13
For more information www.linear.com/LTM8049
LTM8049
APPLICATIONS INFORMATION
stillairalthoughnaturalconvectioncausestheairtomove.
This value is determined with the part mounted to a JESD
51-9 defined test board, which does not reflect an actual
application or viable operating condition.
Giventhesedefinitions,itshouldnowbeapparentthatnone
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
θ
is the thermal resistance between the junction
JCbottom
andbottomofthepackagewithallofthecomponentpower
dissipation flowing through the bottom of the package. In
the typical µModule converter, the bulk of the heat flows
out the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
A graphical representation of these thermal resistances
is given in Figure 3.
θ
isdeterminedwithnearlyallofthecomponentpower
The blue resistances are contained within the µModule
converter, and the green are outside.
JCtop
dissipation flowing through the top of the package. As the
electricalconnectionsofthetypicalµModuleconverterare
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junc-
The die temperature of the LTM8049 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8049. The bulk of the heat flow out of the LTM8049
is through the bottom of the μModule converter and the
BGA pads into the printed circuit board. Consequently a
poor printed circuit board design can cause excessive
heating, resulting in impaired performance or reliability.
Please refer to the PCB Layout section for printed circuit
board design suggestions.
tion to the top of the part. As in the case of θ , this
JCbottom
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θ
JB
is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θ
and the thermal resistance of the
JCbottom
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
8049 F03
µMODULE DEVICE
Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients
8049f
14
For more information www.linear.com/LTM8049
LTM8049
TYPICAL APPLICATIONS
±±5V Converve
MaximumVLCadV ueevorVnsV5IN
2.0
1.5
1.0
0.5
0
V
V
OUT1P
IN1
V
V
OUT1
IN
2.7V TO 15V
5V
4.7µF
FBX1
RUN1
×2
45.3k
RT1
V
47µF
OUT1N
107k
750kHz
CLKOUT1
SYNC2
RT2
LTM8049
107k
750kHz
V
V
OUT2P
IN2
147µF
FBX2
RUN2
60.4k
V
OUT2
SYNC1
V
OUT2N
–5V
0
5
10
15
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2, SHARE1, SHARE2
8049 TA02a
V
(V)
IN
8049 TA02b
PaeallvlV85VOurpursVfCeVIocevasvdV ueevor
MaximumVLCadV ueevorVnsV5IN
V
V
OUT1P
IN1
V
IN
3.5
2.5
1.5
0.5
2.7V TO 20V
4.7µF
FBX1
RUN1
×2
82.5k
RT1
V
OUT1N
80.6k
1MHz
CLKOUT1
SYNC2
V
OUT
SHARE1
8V
LTM8049
SHARE2
RT2
80.6k
1MHz
V
V
OUT2P
IN2
FBX2
RUN2
82.5k
47µF
SYNC1
V
OUT2N
0
5
10
(V)
15
20
V
IN
8049 TA03b
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2
8049 TA03a
8049f
15
For more information www.linear.com/LTM8049
LTM8049
PACKAGE DESCRIPTION
PioVAssigomvorVTablv
(AeeaogvdVbyVPioVNumbve)
PINVNAME
PINVNAME
PINVNAME
PINVNAME
PINVNAME
PINVNAME
F1 GND
A1
A2
V
OUT1P
V
OUT1P
B1
B2
V
V
C1 FBX1
D1
D2
V
V
E1
E2
V
V
OUT1P
OUT1P
OUT1N
OUT1N
OUT1N
OUT1N
C2
V
F2 GND
OUT1N
A3 GND
A4 GND
B3 GND
B4 GND
B5 GND
B6 GND
B7 RUN1
C3 GND
C4 GND
C5 GND
C6 GND
C7 SS1
D3 GND
D4 GND
D5 GND
D6 PG1
D7 SYNC1
E3 GND
E4 GND
E5 GND
F3 SHARE1
F4 SHARE2
F5 GND
A5
A6
A7
V
IN1
V
IN1
V
IN1
E6 CLKOUT1 F6 GND
E7 RT1 F7 GND
PINVNAME
PINVNAME
PINVNAME
J1 FBX2
J2
PINVNAME
PINVNAME
G1
G2
V
V
H1
H2
V
V
K1
K2
V
OUT2P
V
OUT2P
L1
L2
V
V
OUT2N
OUT2N
OUT2N
OUT2N
OUT2P
OUT2P
V
OUT2N
G3 GND
G4 GND
G5 GND
H3 GND
H4 GND
H5 GND
J3 GND
J4 GND
J5 GND
J6 GND
J7 SS2
K3 GND
K4 GND
K5 GND
K6 GND
K7 RUN2
L3 GND
L4 GND
L5
L6
L7
V
IN2
V
IN2
V
IN2
G6 CLKOUT2 H6 PG2
G7 RT2 H7 SYNC2
PACKAGE PHOTO
8049f
16
For more information www.linear.com/LTM8049
LTM8049
PACKAGE DESCRIPTION
PlvasvVevfveVrCVhrrp://www.liovae.cCm/peCducr/LTM8049#packagiogVfCeVrhvVmCsrVevcvorVpackagvVdeawiogs.
BGA Package
77-Lead (15.00mm × 9.00mm × 2.42mm)
(Reference LTC DWG# 05-08-1964 Rev A)
Z
SEE NOTES
DETAIL A
A
aaa
Z
7
E
Y
G
A2
X
SEE NOTES
3
PIN 1
A1
A
B
C
D
E
F
ccc
Z
PIN “A1”
CORNER
4
b1
MOLD
CAP
b
SUBSTRATE
H1
D
F
H2
G
H
J
DETAIL B
e
Øb (77 PLACES)
K
L
ddd
eee
M
M
Z
Z
X Y
aaa
Z
7
6
5
4
3
2
1
PACKAGE TOP VIEW
PACKAGE BOTTOM VIEW
DETAIL B
PACKAGE SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
DETAIL A
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
4
BALL DESIGNATION PER JESD MS-028 AND JEP95
DIMENSIONS
NOM
2.42
0.60
1.82
0.75
0.63
15.00
9.00
1.27
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
SYMBOL
A
A1
A2
b
b1
D
E
MIN
MAX
2.62
0.70
1.92
0.90
0.66
NOTES
0.630 0.025 Ø 77ꢀ
6.350
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
6.350
2.22
0.50
1.72
0.60
0.60
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
7
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
e
F
G
12.70
7.62
0.32
H1
H2
aaa
bbb
ccc
ddd
eee
0.27
1.45
0.37
1.55
0.15
0.10
0.20
0.30
0.15
1.50
LTMXXXXXX
µModule
COMPONENT
PIN “A1”
SUGGESTED PCB LAYOUT
TOP VIEW
TOTAL NUMBER OF BALLS: 77
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
BGA 77 0114 REV A
8049f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
17
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM8049
TYPICAL APPLICATION
PaeallvlVOurpursVrCVIocevasvV–±5VOurpurV ueevor
MaximumVLCadV ueevorVnsV5IN
4
V
V
OUT1P
IN1
V
100µF
×2
IN
2.7V TO 15V
4.7µF
×2
FBX1
RUN1
60.4k
RT1
V
OUT1N
107k
750kHz
CLKOUT1
3
2
1
0
SYNC2
SHARE1
LTM8049
SHARE2
RT2
107k
750kHz
V
V
IN2
OUT2P
FBX2
RUN2
60.4k
V
OUT
–5V
SYNC1
V
OUT2N
0
5
10
(V)
15
20
8049 TA04a
V
IN
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2
8049 TA04b
DESIGN RESOURCES
SUBJE T
DES RIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PARTVNUMBER DES RIPTION
OMMENT
LTM8045
LTM8046
Single. Inverting or SEPIC µModule DC/DC Convertor
2.8 ≤ V ≤ 18V. 2.5V ≤ V
≤ 15V. 6.25mm ꢀ 11.25mm ꢀ 4.92mm BGA
IN
OUT
2kVAC, 2.75W Isolated DC/DC µModule Converter
3.1V ≤ V ≤ 31V, 1.8V ≤ V
≤ 12V. 5V at 550mA from 24V ,
IN
OUT
IN
9mm ꢀ 15mm ꢀ 4.92mm BGA
LTM8047
LTM8048
725kVDC, 1.5W Isolated DC/DC µModule Converter
3.1V ≤ V ≤ 32V, 2.5V ≤ V
≤ 12V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA
OUT
IN
725kVDC, 1.5W Isolated DC/DC µModule Converter with 3.1V ≤ V ≤ 32V, 1.2V ≤ LDO V
Integrated LDO
≤ 12V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA
IN
OUT
LTM8067
LTM8068
2kVAC, 2.25W Isolated DC/DC µModule Converter
2.8V ≤ V ≤ 40V, 2.5V ≤ V
≤ 24V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA
IN
OUT
2kVAC, 2.25W Isolated DC/DC µModule Converter with
Integrated LDO
2.8V ≤ V ≤ 40V, 1.2V ≤ LDO V
≤ 18V. 9mm ꢀ 11.25mm ꢀ 4.92mm BGA
IN
OUT
LTM8023
LTM8053
36V , 2A, Step-Down DC/DC µModule Converter. Can Be 3.6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V. 9mm x 11.25mm x 2.82mm LGA.
IN
IN
OUT
Used for Inverting
9mm x 11.25mm x 3.52mm BGA
40V , 3.5A Step-Down DC/DC µModule Regulator. Can
3.4V ≤ V ≤ 40V. 0.97V ≤ V ≤ 15V. 6.25mm x 9mm x 3.32mm BGA.
IN
IN
OUT
be used for inverting.
8049f
LT 0816 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
●
●
LINEAR TECHNOLOGY CORPORATION 2016
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM8049
相关型号:
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